Friday, 2 November 2012

VHDL Course

introduction to VHDL

The VHSIC (Very High Speed Integrated Circuits) Hardware Description Language is an industry standard language used to describe hardware from the abstract to the concrete level. In 1986, VHDL was proposed as an IEEEstandard. It went through a number of revisions and changes until it was adopted as the IEEE 1076 standard in December 1987, Then VHDL 1076-1993 and the latest VHDL 1076-2002.

Here I introduce an easy introduction Course to VHDL divided in 6 parts :

Part-1 : Introducing VHDL. (Download Here)
  • Introduction.
  • Levels of representation.
  • Structure of a VHDL file.
Part-2 : Modeling in VHDL. (Download Here)
  • Behavioral Modeling.
  • Sequential Modeling.
Part-3 : Concurrent Statements. (Download Here)
  • Simple Concurrent Signal Assignments.
  • Conditional Signal Assignments.
  • Selected Signal Assignments.
  • Structural Modeling.
  • Component Declaration.
  • Component Instantiation.
Part-4 : Data objects. (Download Here)
  • Constants.
  • Variables.
  • Signals.
  • Signals vs. Variables.
Part-5 : Combinational Circuit Design Example. (Download Here)
  • Full Adder Circuit.
Part-6 : Sequential Circuit Design Example. (Download Here)
  • Counter using JK Flip-Flops.

ALTERA VHDL Online Course

Altera made a nice presentation for learning the basics of the VHDL language in just 1.5 hours and it's for free, you need only to register and you can run the course online .

>> Objectives of the course :
  1. Construct complete VHDL models .
  2. Generate Logic functions using the VHDL .
  3. Create hierarchical VHDL designs.
>> Course outlines:
  1. VHDL introduction.
  2. Design units.
  3. Architecture modeling fundamentals.
  4. VHDL logic synthesis.
  5. Hierarchical designing.

Please feel free to leave a comment if there is a dead link or a problem with the links.

1 comment:

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