Digital Design Using VHDL Course

Course Outlines

• Introduction to VHDL
• Statements in VHDL
• Sequential Statements
• Concurrent Statements
• Data Objects
• Data Operators
• Data types
• FSM finite state machines
• Structural Description
• Testbench
• Introduction to FPGA
• Implementation on FPGA

Tools Used during course

You can download this course here :

Introduction to the Course

Session 1

- Introduction to VHDL
- ASIC & FPGA Design flow
- How to read and write VHDL code
- Library and package
- Entity
- Basic data types
- Architecture

Session 2

- Combinational vs Sequential 

- Data Objects

     - Signals

- VHDL Statements

     - Sequential Statements

        - What is Process 

        - IF Statement

        - CASE Statement

- Combinational Logic

- Sequential Logic

Session 3

- Concurrent Statements

      1-Assign Statement 

      2-Process

      3-When-else

      4-With-select

- Data Objects

      1-Signals

      2-Variables

      3-Constants

Session 4

- Data Operators

      - Aggregate

      - Concatenation

      - Attributes

Session 5

- Data Types

      - Scalar

      - Composite

      - User defined

Session 6

- Finite State Machine

      - What is FSM?

      - Moore machine

      - Mealy machine

      - FSM in VHDL

Session 7

- Structural Description

- Generic Statements

- Packages

- Generate Statements

            -For Generate

Session 8

- Arithmetic Circuits

- Tutorial [2] 

        - IP Cores

        - ISIM Simulator

        - Language Templates

- VHDL Coding TIPS

Session 9

- Sequential Statements

      - Loops For-While

      - Next-Exit Statements

      - Wait Statement

      - Null Statement

      - Assert Statement

      - Functions

      - Procedures 

- Test Benches

- Dealing with Files

- Modelsim and Do Files

Session 10

- Test bench example

- ASIC & FPGA Design flow

- implementation phases 

- FPGA Architecture

      - Demo programming FPGA SP3

- FIFO

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